Description

VLSI technology is to optimize the any type of digital architecture. Because this type of optimization process is mainly used to enhance the various applications. Adder architecture is to present the more type of digital core architecture and to control the system functionality level. The adder architecture is to improve any digital architecture performance. We focus the different type of adder architecture in physical level and to modify the carry selection process in internal architecture level. ADDERS are a key building block in arithmetic and logic units and hence increasing their speed and reducing their power/energy consumption strongly affect the speed and power consumption of processors. There are many works on the subject of optimizing the speed and power of these units, which have been reported in. Obviously, it is highly desirable to achieve higher speeds at low-power/energy consumptions, which is a challenge for the designers of general purpose processors. In this architecture, our work is to develop the 32-bit adder architecture and to check the carry selection processing time. This adder architecture is to implement the carry skip adder technique and this technique is to reduce the power consumption. The proposed system is to design a 32-bit carry skip adder architecture in dsch2 software. This technique is to reduce the internal gate count based on Boolean equation. The proposed system is to optimize 32-bit CSKA adder architecture compare to the existing system. Because this modification process is mainly used to carry propagation level. The proposed system path delay to be reduced compare to existing system. And this system requires low complexity.