Description

     The digital architecture is mainly used in all type of real world application architectures and thus the architecture to modify based on the enhancement purpose. The VLSI technology is to optimize the any type of digital architecture. Hardware acceleration has been demonstrated an extraordinarily assuring fulfilment technique for the digital signal processing. In this proposed work commence innovative accelerator architecture containing adjustable computational units that reinforce the execution of a large set of operation patterning found in digital signal processing kernels. The proposed system is computation of flexible accelerator is performed by using of advanced carry save arithmetic concept such as recording techniques. Thus provide the enabling of CS optimization to be performed over than conventional methods. Carry save adder is the design of a high speed multioperand adder.it consumes three n-bit input integers to be added and produces two outputs n-bit partial sum and n-bit carry. Unlike the normal adders such as ripple carry adder, a CSA consists of multiple one-bit full adders without any carry chaining. The polynomial algorithm is used to reduce the time delay which automatically leads the speed increasing ratio. The Multi-dimensional signal processing scheme improves the control unit to control the entire mux unit and register bank. A domain-specific architecture generation algorithm is used to improve the acceleration of DSP.The proposed flexible DSP accelerator architecture produces moderate achievement of up to 61.91% in area-delay product and 54.43% in energy consumption over the conventional topology.