VLSI-FPGA

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Precharge-Free, Low-Power Content-Addressable Memory

₹4,500.00

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Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

₹3,000.00

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Rapidly Tunable Dual-Comb RF Photonic Filter for Ultrabroadband RF Spread Spectrum Applications

₹4,500.00

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Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory

₹3,000.00

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Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs

₹4,500.00

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Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

₹4,500.00

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Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches

₹3,500.00

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Resource Shared Crypto Coprocessor of AES Enc Dec With SHA 3

Original price was: ₹6,000.00.Current price is: ₹5,500.00.

-8%Off

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Shield: A Reliable Networ k-on-Chip Router Architecture for Chip Multiprocessors

₹4,500.00

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simplifying Clock Gating Logic by Matching Factored Forms

₹3,000.00

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Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

₹4,500.00

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Single Event Performance of Sense Amplifier Based Flip Flop Design in a 16 nm Bulk FinFET CMOS Process

₹3,500.00

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Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell

₹4,500.00

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Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes

₹3,000.00

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Smart Reliable Network-on-Chip

₹3,000.00

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Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks

₹3,000.00

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Timing Error Tolerance in Small Core Designs for SoC Applications

₹4,500.00

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TOWARD MULTI-GIGABIT WIRELESS: DESIGN OF HIGH-THROUGHPUT MIMO DETECTORS WITH HARDWARE-EFFICIENT ARCHITECTURE

₹3,000.00

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Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology

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Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications

₹4,500.00

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VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library

₹6,000.00

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VLSI Implementation of a Cost-Efficient Micro Control Unit with an Asymmetric Encryption for Wireless Body Sensor Networks

₹3,500.00

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Wide-Range Adaptive RF-to-DC Power Converter for UHF RFIDs

₹4,500.00

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Symptom Based Explainable Artificial Intelligence Model for Leukemia Detection

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Symptom Based Explainable Artificial Intelligence Model for Leukemia Detection

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Symptom Based Explainable Artificial Intelligence Model for Leukemia Detection

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VLSI-FPGA

Precharge-Free, Low-Power Content-Addressable Memory

Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

Rapidly Tunable Dual-Comb RF Photonic Filter for Ultrabroadband RF Spread Spectrum Applications

Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory

Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches

Resource Shared Crypto Coprocessor of AES Enc Dec With SHA 3

Shield: A Reliable Networ k-on-Chip Router Architecture for Chip Multiprocessors

simplifying Clock Gating Logic by Matching Factored Forms

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

Single Event Performance of Sense Amplifier Based Flip Flop Design in a 16 nm Bulk FinFET CMOS Process

Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell

Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes

Smart Reliable Network-on-Chip

Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks

Timing Error Tolerance in Small Core Designs for SoC Applications

TOWARD MULTI-GIGABIT WIRELESS: DESIGN OF HIGH-THROUGHPUT MIMO DETECTORS WITH HARDWARE-EFFICIENT ARCHITECTURE

Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology

Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications

VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library

VLSI Implementation of a Cost-Efficient Micro Control Unit with an Asymmetric Encryption for Wireless Body Sensor Networks

Wide-Range Adaptive RF-to-DC Power Converter for UHF RFIDs

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Symptom Based Explainable Artificial Intelligence Model for Leukemia Detection

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Symptom Based Explainable Artificial Intelligence Model for Leukemia Detection

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VLSI-FPGA

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