Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes
Rs3,000.00
10000 in stock
SupportDescription
Sliced Message Passing (SMP), is introduced. The key idea is to slice the total set of variable-to-check messages into equal-sized chunks, then to perform check-node computation sequentially chunk by chunk. The hardware architectures of SMP decoding are introduced. Each check-node processing unit of the proposed register-based parellel architecture has only inputs instead of inputs. An optimized SMP decoder has been further implemented for a 2048-bit (6, 32) LDPC decoder of the emerging IEEE 10 G Base-T standard in an IBM CMOS 90-nm process. A synthesis tool called QCSyn is described, which takes the matrix of a quasi-cyclic LDPC code and the resource characteristics of an FPGA and automatically synthesizes a vector or folded architecture that maximizes the decoding throughput for the code on the given FPGA by selecting the appropriate degree of folding and/or vec- torization. This helps not only in reducing the design time to create a decoder but also in quickly retargeting the implementation to a different (perhaps new) FPGA or a different emulation board
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