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1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS
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3,000.00
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A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process
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4,500.00
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A 40–170 MHz PLL-Based PWM Driver Using2-/3-/5-Level Class-D PA in 130 nm CMOS
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4,500.00
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A Colpitts CMOS Quadrature VCO Using Direct Connection of Substrates for Coupling
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3,000.00
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A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
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4,500.00
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A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
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4,500.00
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A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic
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4,500.00
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A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones
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4,500.00
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A Low-Power Robust Easily CascadedPentaMTJ-Based Combinational and Sequential Circuits
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4,500.00
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A New XOR-Free Approach for Implementation of Convolutional Encoder
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4,500.00
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A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO
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4,500.00
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A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell
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4,500.00
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Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes
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4,500.00
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An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors
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4,500.00
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An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code
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4,500.00
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Analysis and Design of an E-Band Transformer-Coupled Low-Noise Quadrature VCO in 28-nm CMOS
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4,500.00
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Analysis and Design of an Ultrabroadband Stacked Power Amplifier in CMOS Technology
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4,500.00
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Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC
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4,500.00
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Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers
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4,500.00
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Computing Seeds for LFSR-Based Test Generation From Nontest Cubes
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4,500.00
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Detection of Superpoints Using a Vector Bloom Filter
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4,500.00
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Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip
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4,500.00
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Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
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4,500.00
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Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC
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4,500.00
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High sensitivity CMOS RF-DC converter in HF RFID Band
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4,500.00
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New
High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators
₹
6,000.00
PROJ20238
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High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m)
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4,500.00
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High-Power CMOS Current Driver With Accurate Transconductance for Electrical Impedance Tomography
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3,000.00
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High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
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4,500.00
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Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage
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3,000.00
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Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
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4,500.00
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LUT Optimization for Distributed Arithmetic-B Block Least Mean Square Adaptive Filter
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4,500.00
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MACS: A Highly Customizable Low-Latency Communication Architecture
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4,500.00
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Modeling and design of EMI-Immune opamps in 0.18-um CMOS technology
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4,500.00
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Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs
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4,500.00
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Tunable CMOS Delay Gate With Improved Matching Properties
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3,000.00
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