Description

The increasing number of cores on a chip has made the networ k on chip (NoC) concept the standard communicationparadigm for chip multiprocessors. A fault in an NoC leads to undesirable ramifications tha t can severely impact the perfor mance of a chip. Therefore, it is vital to design fault tolerant NoCs. In this paper, we present Shield , a reliable NoC router architecture that has the unique ability to tolerate both hard and soft er rors in the routing pipeline using techniques such as spati al redundancy, exploitation of idle cycles, bypassing of faulty resources and selective hardening. Using Mean Time to Failure and Silicon Protection Factor metrics, we show tha t Shield is six times more reliable than the baseline-unprotected router and is a t least 1.5 times more reliable than existing fault tolerant router architectures. We introduce a new metric called Soft Er ror Improvement Factor and show tha t the soft error tolerance of Shield has improved by three times in comparison to the baseline-unprotected router. This reliability improvement is accomplished by incur ring an area and power overhead of 34 and 31 percent respectively. La tency analysis using SPLASH-2 and PARSEC reveals that in the presence of faults, lat ency increases by a modest 13 and 10 percent respectively