Description

In this paper, we suggest a novel approach to designing fully depleted silicon-on-insulator (FDSOI) FET-based dynamic logic circuits. By adjusting the back gate (BG) bias, FDSOI FETs can switch between low-Vt and high-V states in terms of threshold voltage (V). Our design presents dynamic logic gates (such NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like a half-adder and full-adder) and uses the front gate (FG) and back gate (BG) of an FDSOI FET as the input terminals. We design a NAND and NOR gate for the design of the half adder and full adder. This gates are basically used for the FET circuits so far we design a basic circuits using the CMOS technology using the 90 mmm technology. Finally calculate the transient response for the gate circuits and also plot the graph for the truth table.