Description

The influence of electronics in pervasive computing needs confidentiality of the electronically processed and transmitted data. The threat of DPA attacks is of crucial importance when designing cryptographic hardware. As a result, several DPA counter-measures at the cell level have been proposed in the last years, but none of them offers perfect protection against DPA attacks. Moreover, all of these DPA-resistant logic styles increase the power consumption and the area consumption significantly. The rapid growth of portable electronic device is increased and they are designed with low power and high speed is critical. Thus the low power and high speed can be achieved by designing the circuit in systematic cell methodology. Thus this systematic cell methodology design achieves high speed and low power. We focus the different type of adder architecture in physical level and to modify carry selection and to optimize the no of register element. Our proposed work is to design a 8-bit adder design using three input XOR and XNOR gates. Thus the systematic cell design methodology can be achieved by implementing transmission gate. By this type of designing the low power and high speed can achieved. Thus this type of three input XOR/XNOR gates is realized using the transmission gate based logic. Then this type of gates is operating in high speed and they are operating in low power. Thus the circuit size will be reduced. Proposed method is to design a three-input XOR/XNOR based 8-bit adder architecture. This architecture is used to maintain summation results for after completing addition process. The size of the circuit is reduced. To reduce the overall leakage power level.