A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers. Comparators are used in central processing unit s and microcontrollers. Quantum dot cellular automata referred to simply the high performance technology in digital circuits. The binary comparator to optimize the pattern gate count in the regular comparator architecture based on the majority gate process. This scheme designed to contraption in QCA the novel equations proved. The first recommended comparator exploitations a cascade-based (CB) manners. The design difficulty of the comparators perceived is reported in terms of number of MGs and inverters need in the general designs, and number of MGs within the lowliest computational paths. The new strategy has been exploited in the design of two different comparator architectures and for several operands word lengths. With respect to existing counterparts, the comparators proposed here exhibit significantly higher speed and reduced overall area. The experimental device is a four-dot QCA cell with two electrometers. The dots are metal islands, which are coupled by capacitors and tunnel junctions. An improved design of the cell is presented in which all four dots of the cell are coupled by tunnel junctions. A noninvasive electrometer is presented which improves the sensitivity and linearity of dot potential measurements.