Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
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A comparator is a device that compares two voltages or currents and provides the outputs which is larger. A comparator used to maximize the speed and power efficiency of ADC’s (Analog to Digital converters). Comparator has two input terminals and one output terminal. In this, They proposed comparator and the comparator is modified in circuit level by adding few transistors, for low-power consumption. The whole design is based on CMOS Technology. Because CMOS technology offers less power dissipation, smaller noise margins, and higher packing density. Here, the analysis on delay of the comparator is presented. The double tail modification provides the low power consumption and fast operation even in small supply voltage. By adding few transistors they reduced delay time also. The reduction of delay time will provide power consumption. By this design they achieved some power consumption. But they modified the circuit added transistors, that may consume some powers. so we have to concentrate on complexity or to reduce the power consumption. Hence we are going to propose a design of CMOS comparator based on Low voltage bipolar sizing CMOS technique. By the design they have achieved small amount of power consumption. And they reduce the required supply voltage which provided for delay time. We focus to design architecture of CMOS comparator using Low voltage bipolar sizing CMOS technique. That means, Our proposed design of the Comparator design is based on bipolar CMOS technology. This is the combination of Bipolar and CMOS technology. The Bipolar CMOS circuit offers high speed, high gain, and low output resistance, which are excellent properties for high-frequency analog amplifiers, and CMOS technology offers high input resistance and is excellent for constructing simple, low-power logic gates. Hence we chose bipolar method. Two voltage/Sources are applied to the designed architecture that compares both inputs and resulting the higher source as output. Finally our proposed system provides the reduced delay time and results in low power consumption.
Tags: 2014, Domain > Network Projects