Description

XOR Free Encoder means error correcting codes. This work is to implement the partial parallel encoder and decoder architecture. Because the real time data transmission and reception process is consist the more no of binary bit based transformation and it accurs the more no of error in bit transformation due to data transmission and reception process. Our work is to reduce the encoder and decoder architecture complexity and time level, so we apply the XOR Free Encoder technique based partial parallel encoder and decoder architecture. Because the fully parallel encoder and decoder architecture is need more circuit complexity based on critical path delay time. So we modify the partial parallel encoder and decoder architecture using XOR Free Encoder technique. The encoder and decoder architecture is consists of 4-stage section unit. This encoder is consists of xor-gate, mux and register component. This architecture is to reduce the circuit complexity and to reduce the critical path section. So it reduces the error level in bit wise data transmission and reception process. The encoder architecture 1^st stage work is to implement the xor gate operation. This operation is used to identify the minimum distance value and to apply the 2^nd stage level. This level is to calculate the minimum distance between 1^st stage output data bits and to apply the next stage. This stage is to store the previous stage output section and to apply the key selection bit and to implement the xor gate operation between previous stage store data bit and direct data bit and to again store the output value. This work is to reduce the bit losses in data transmission and reception level. Then to pass the 4^th stage unit process is same like a 3^rd stage processing architecture. Finally to get the encoder output data bits using partial parallel architecture. Our decoder architecture process is to inverse architecture operation based encoder architecture and to get the data bits effectively.