VLSIHut
0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier
A simple high-performance architecture for bulkdriven operational transconductance amplifiers (OTA..
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
We present, in this paper, a new 10T static random access memory cell having single ended decoupled..
A 0.45-V Low-Power OOK/FSK RF Receiver in 0.18 µm CMOS Technology for Implantable Medical Applications
A 0.45-V low-power 0.18 ?m CMOS OOK/FSK RF receiver for implantable medical applications is propos..
A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process
A 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity,..
A 32 kb 0.35 1.2 V, 50 MHz 2.5 GHz Bit-Interleaved SRAM with 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS
An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage..
A 40–170 MHz PLL-Based PWM Driver Using2-/3-/5-Level Class-D PA in 130 nm CMOS
A high-speed driver that provides a pulsewidth modulated output while using a class-D Power Amplif..
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC
Now days the usage of continuous-time incremental sigma-delta ADC in neural recording system is in..
A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current-Mode Controlled Switching Regulators
A one-pin mode transition circuit that addresses the issues related to clock synchronization..
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient
Reconfigurable digital filter is being widely used in applications such as communication and signa..
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
Integral histogram image can accelerate the computing process of feature algorithm in computer vis..
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply
A new power-efficient electrocardiogram acquisition system that uses a fully digital architecture ..
A graph based algorithm to minimize total wire length in vlsi channel routing
The important problem in VLSI layout design is minimization of total wire length. Minimization of wi..
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
Transpose form finite-impulse response (FIR) filters are inherently pipelined and support mu..
A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic
A high-throughput energyefficient Successive Cancellation (SC) decoder architecture for polar code..
A Low Energy Machine Learning Classifier Based on Clocked Comparators for Direct Inference on Analog Sensors
This paper presents a system, where clocked comparators consuming only CV2 energy directly derive ..