Your shopping cart is empty!
Hi there! Click one of our representatives below and we will get back to you as soon as possible.
A modified bit-reliability based decoding algorithm
is presented based on a recent work by Huang e..
We design a hardware and energy-efficient stochastic
lower–upper decomposition (LUD) scheme for mu..
VLSI technology is to optimize the any type of
digital architecture. Because this type of optimizat..
A high-speed, low-power, and highly reliable
frequency multiplier is proposed for a delay-locked l..
The objective of Video/image compression is to reduce irrelevance and redundancy of the Video/image ..
Hybrid configurable logic block architectures for
field-programmable gate arrays that contain a mi..
Coarse-grained reconfigurable architecture (CGRA) is
a promising architecture with high performanc..
An on-line transparent test technique for detection
of latent hard faults which develop in firstin..
In this paper we present the FPGA-based framework IFDAQ which is used for the development of data ac..
In this process we implement the novel two low power-delay-product (PDP) of dynamic circuit based CM..
digital architecture is mainly used in all type of real world application
architectures and th..
The wire sensor network used to the data transmission process and to optimize the time and increase ..
A fully integrated electrocardiogram (ECG) signal
processor (ESP) for the prediction of ventricula..
Split-radix fast Fourier transform (SRFFT) is an
ideal candidate for the implementation of a low-p..
A low-power technique to reduce the power
consumption of the dynamic comparators is presented. Usi..