VLSI-FPGA
Hard-Information Bit-Reliability Based Decoding Algorithm for Majority-Logic Decodable Nonbinary LDPC Codes
A modified bit-reliability based decoding algorithm is presented based on a recent work by Huang e..
Hardware and Energy-Efficient StochasticLU Decomposition Scheme for MIMO Receivers
We design a hardware and energy-efficient stochastic lower–upper decomposition (LUD) scheme for mu..
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
VLSI technology is to optimize the any type of digital architecture. Because this type of optimizat..
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked l..
High-throughput-pipelined-2D-Discrete-cosine-transform-for-video-compression
The objective of Video/image compression is to reduce irrelevance and redundancy of the Video/image ..
Hybrid LUT/Multiplexer FPGA Logic Architectures--XILINX
Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mi..
Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures
Coarse-grained reconfigurable architecture (CGRA) is a promising architecture with high performanc..
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
An on-line transparent test technique for detection of latent hard faults which develop in firstin..
Intelligent FPGA Data Acquisition Framework
In this paper we present the FPGA-based framework IFDAQ which is used for the development of data ac..
Low power delay product dynamic CMOS circuit design techniques
In this process we implement the novel two low power-delay-product (PDP) of dynamic circuit based CM..
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
The digital architecture is mainly used in all type of real world application architectures and th..
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
The wire sensor network used to the data transmission process and to optimize the time and increase ..
Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
A fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricula..
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-p..
Low-power technique for dynamic comparators
A low-power technique to reduce the power consumption of the dynamic comparators is presented. Usi..