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VLSI Design for SVM-Based Speaker Verification System

VLSI Design for SVM-Based Speaker Verification System

Starting at: Rs.4,500.00

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VLSI Design for SVM-Based Speaker Verification System

 The chip implementation of a support vector machine (SVM)-based speaker verification system. The proposed chip comprises a speaker feature extraction (SFE) module, an SVM module, and a decision module. The SFE module performs autocorrelation analysis, linear predictive coefficient (LPC) extraction, and LPC-to-cepstrum conversion. The SVM module includes a Gaussian kernel unit and a scaling unit. The purpose of the Gaussian kernel unit is first to evaluate the kernel value of a test vector and a support vector. Four Gaussian kernel processing elements (GK-PEs) are designed to process four support vectors simultaneously. Each GK-PE is designed in the pipeline fashion and is capable of performing 2-norm and exponential operations. An enhanced CORDIC architecture is proposed to calculate the exponential value. As well as the Gaussian kernel unit, a scaling unit is also developed for use in the SVM module. The scaling unit is used to perform scaling multiplications and the remaining operations of SVM decision value evaluation.


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  • Model: PROJ5044
  • 999 Units in Stock
  • Manufactured by: ClickMyProjects

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This product was added to our catalog on Wednesday 07 September, 2016.