VLSI-FPGA
Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks
The testing architecture mainly used in all type of real world application architectures and thus th..
3,000.00INR
Timing Error Tolerance in Small Core Designs for SoC Applications
Timing errors are an increasing reliability concern in nanometer technology, high complexity and m..
4,500.00INR
TOWARD MULTI-GIGABIT WIRELESS: DESIGN OF HIGH-THROUGHPUT MIMO DETECTORS WITH HARDWARE-EFFICIENT ARCHITECTURE
MIMO-OFDM is the foundation for most advanced wireless local area network (Wireless LAN) and mobile ..
3,000.00INR
Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology
Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and..
4,500.00INR
Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications
Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. Th..
4,500.00INR
VLSI Implementation of a Cost-Efficient Micro Control Unit with an Asymmetric Encryption for Wireless Body Sensor Networks
This paper presents a very large-scale integration (VLSI) circuit design of a micro control unit (M..
3,500.00INR
Wide-Range Adaptive RF-to-DC Power Converter for UHF RFIDs
A wide-range, differential, cross-coupled rectifier is proposed with an extended dynamic range of ..
4,500.00INR