VLSI-FPGA
Precharge-Free, Low-Power Content-Addressable Memory
Content-addressable memory (CAM) is the hardware for parallel lookup/search. The parallel search s..
Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count
In our project we analyze the performance of orthogonal wavelet filters for image compression on var..
Rapidly Tunable Dual-Comb RF Photonic Filter for Ultrabroadband RF Spread Spectrum Applications
We demonstrate a rapidly frequency-tunable radio frequency (RF) filter using microwave photonics t..
Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory
Due to higher integration densities, technology scaling and variation in parameters, the performance..
Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs
It is necessary to ensure any leakages which cause the read sensing failure and degrade..
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops
A new approach to reduce dynamic power, leakage, and area of application-specified integrated circ..
Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches
Pulsed latches are gaining increased visibility in low-power ASIC designs. They provide an alternat..
Resource Shared Crypto Coprocessor of AES Enc Dec With SHA 3
Cryptographic co-processors are integral to the modern System-on-Chips. Flexibility in such designs..
Shield: A Reliable Networ k-on-Chip Router Architecture for Chip Multiprocessors
The increasing number of cores on a chip has made the networ k on chip (NoC) concept the standard ..
simplifying Clock Gating Logic by Matching Factored Forms
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dis..
Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology
Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy ef..
Single Event Performance of Sense Amplifier Based Flip Flop Design in a 16 nm Bulk FinFET CMOS Process
The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) design..
Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell
A Schmitt-trigger-based single-ended 11T SRAM cell, which significantly improves read and write st..
Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes
Sliced Message Passing (SMP), is introduced. The key idea is to slice the total set of variable-to-c..
Smart Reliable Network-on-Chip
The network-on-chip (NoC) design problem requires the generation of a power and resource efficient i..