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VLSI-FPGA

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Low-Power-Clock-Distribution-Using-a-Current-Pulsed-Clocked-Flip-Flop

In this proposed system is based on communication process. This design mainly consists three units. ..

4,500.00INR
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Low-Power-Pulse-Triggered-Flip-Flop-Design-Based-on-a-Signal-Feed-Through-Scheme

Flip-flops and latches are used as data storage elements. Such data storage can be used for storage ..

4,500.00INR
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Low‑power-half‑select-free-single‑ended-10-transistor-SRAM-cell

In this proposed implementation design is based on 11T and 12T SRAM cell for automotive electronics ..

4,500.00INR
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MACS: A Highly Customizable Low-Latency Communication Architecture

Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing ..

4,500.00INR
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Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression

A new compression technique of next-iteration initialization metrics for relaxing the storage dema..

4,500.00INR
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Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells

In energy-constrained applications, SRAM systems operating in the subthreshold region are often dep..

3,500.00INR
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Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM

RRobust organ segmentation is a prerequisitefor computer-aided diagnosis, quantitative imaging ana..

4,500.00INR
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Multiplierless Unity-Gain SDF FFTs

A novel approach to implement multiplierless unity-gain single-delay feedback fast Fourier transfo..

4,500.00INR
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New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements

This paper presents novel designs of static dual-edgetriggered (DET) flip-flops that exhibit uniqu..

4,500.00INR
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Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter

An open-loop fractional divider is proposed to eliminate the deterministic jitter caused by the co..

4,500.00INR
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Optimized Active Single Miller Capacitor Compensation With Inner Half Feed for ward Stage for Very High Load Three Stage OTAs

A new effective single-Miller capacitor compensation topology for three-stage amplifiers with very..

4,500.00INR
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Optimized built in self repair for multiple memories

A new built-in self-repair (BISR) scheme is proposed for multiple embedded memories to find optimu..

4,500.00INR
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Partially Repeated SC-LDPC Codes for Multiple-Access Channel

A simple partially repeated spatially coupled low-density parity-check (SC-LDPC) code is proposed ..

4,500.00INR
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Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Power and energy minimization is a critical concern for the battery life, reliability, and yield o..

4,500.00INR
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Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation

In this paper, a pre-charged local bit-line sharing (PCLBS) static random access memory (SRAM) for n..

3,500.00INR
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