VLSI-FPGA
Low-Power-Clock-Distribution-Using-a-Current-Pulsed-Clocked-Flip-Flop
In this proposed system is based on communication process. This design mainly consists three units. ..
Low-Power-Pulse-Triggered-Flip-Flop-Design-Based-on-a-Signal-Feed-Through-Scheme
Flip-flops and latches are used as data storage elements. Such data storage can be used for storage ..
Low‑power-half‑select-free-single‑ended-10-transistor-SRAM-cell
In this proposed implementation design is based on 11T and 12T SRAM cell for automotive electronics ..
MACS: A Highly Customizable Low-Latency Communication Architecture
Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing ..
Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression
A new compression technique of next-iteration initialization metrics for relaxing the storage dema..
Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells
In energy-constrained applications, SRAM systems operating in the subthreshold region are often dep..
Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM
RRobust organ segmentation is a prerequisitefor computer-aided diagnosis, quantitative imaging ana..
Multiplierless Unity-Gain SDF FFTs
A novel approach to implement multiplierless unity-gain single-delay feedback fast Fourier transfo..
New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements
This paper presents novel designs of static dual-edgetriggered (DET) flip-flops that exhibit uniqu..
Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter
An open-loop fractional divider is proposed to eliminate the deterministic jitter caused by the co..
Optimized Active Single Miller Capacitor Compensation With Inner Half Feed for ward Stage for Very High Load Three Stage OTAs
A new effective single-Miller capacitor compensation topology for three-stage amplifiers with very..
Optimized built in self repair for multiple memories
A new built-in self-repair (BISR) scheme is proposed for multiple embedded memories to find optimu..
Partially Repeated SC-LDPC Codes for Multiple-Access Channel
A simple partially repeated spatially coupled low-density parity-check (SC-LDPC) code is proposed ..
Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM
Power and energy minimization is a critical concern for the battery life, reliability, and yield o..
Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation
In this paper, a pre-charged local bit-line sharing (PCLBS) static random access memory (SRAM) for n..