VLSI-FPGA
Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata
A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers...
Design of QPP Interleavers for the ParallelTurbo Decoding Architecture
Parallel interleaver is an indispensable component for the parallel turbo decoder. The ever increa..
Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
Approximate computing has received significant attention as a promising strategy to decrease power..
Designing RF Ring Oscillator Using Current Mode Technology
In this paper, a new method of designing RF ring oscillator using current-mode technology is present..
Dual-Band Waveform Generator With Ultra-Wide Low-Frequency Tuning-Range
A novel mixed-signal low-power dual-band square/triangular waveform generator (WFG) chip with a wi..
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces
Wireless 3-D network-on-chips (NoCs) with inductive-coupling ThruChip interfaces provide a large d..
Efficient Register Renaming and Recovery for High-Performance Processors
An efficient hardware solution to perform table lookup is the content addressable memory (CAM). A CA..
Energy and Area Efficient Three-Input XOR/ XNORs With Systematic Cell Design Methodology
The influence of electronics in pervasive computing needs confidentiality of the electronically proc..
Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories
Error correction code (ECC) and built-in selfrepair (BISR) techniques by using redundancies have b..
Fault-Tolerant-Parallel-Filters-Based-on-Error-Correction-Codes
The power consumption and speed are the two main challenging factors in Very Large Scale Integrated ..
Fixed-Point Computing Element Design for Transcendental Functions and Primary Operations in Speech Processing
A fixed-point architecture based on a reconfigurable scheme for integrating several commonly used ..
FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm
A high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based o..
FPGA-Based-Implementation-&-Power-Analysis-of-Parameterized-Walsh-Sequences
The digital architecture is mainly used in all type of real world application architectures and thus..
Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators
Ring oscillators (ROs) are popular due to their small area, modest power, wide tuning range, and e..
Fully Integrated 10-GHz Active Circulator and Quasi-Circulator Using Bridged-T Networks in Standard CMOS
A three-port active circulator and an active quasicirculator (QC) based on bridged-T networks (BTN..