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Low-power technique for dynamic comparators

Product Code:PROJ7227
Availability:In Stock
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  • 4,500.00INR

A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-amplification phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%.

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Tags: VLSI-Verilog-VHDL-Xillinx-CMOS-TannerTool-FPGA

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