Low power delay product dynamic CMOS circuit design techniques
In this process we implement the novel two low power-delay-product (PDP) of dynamic circuit based CMOS design. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP. The operating voltage will be reduced to 1.4 V in dynamic circuit logics. Simulation results indicate that the proposed techniques can improve circuit PDP. This process implemented by using Tanner EDA tool and implementation technology is 25 nm (CMOS Technology). The NAND gate AND gate implementation is done by using the PMOS and NMOS devices. These are working based on the clock signal (pre-charge and evaluation phase).
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