Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
The digital architecture is mainly used in all type of real world application architectures and thus the architecture to modify based on the enhancement purpose. The VLSI technology is to optimize the any type of digital architecture. Multiplication is an important fundamental function in arithmetic logic operation. Computational performance of a DSP system is limited by its multiplication performance and since, multiplication dominates the execution time of most DSP algorithms. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. The proposed topology is used configurable carry save adder that avoid the unnecessary carry save addition operations. The extra clock cycles is reduced by using of CCSA. The proposed Montgomery modulus multiplier method produce high performance and low hardware complexity. The full carry save based mm multiplier overcome the conventional semi carry save based mm multiplier. The proposed multiplier can be used for low - power applications and significant area–time product improvement when compared with existing designs. The architecture makes use of a low configurable carry save adder based Montgomery modulus multiplier proposed in this work.
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