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VLSI-CMOS

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Partially Parallel Encoder Architecture for Long Polar Codes

AbstractPOLAR code means error correcting codes. This work is to implement the partial parallel enco..

3,500.00INR
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Performance Analysis and Optimization for Homogenous Multi core System based on 3D Torus Network on Chip

Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip comm..

3,500.00INR
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Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV

Low power dissipation, low leakage current, low cost and there is required to reduce each of these. ..

3,000.00INR
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Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs

 It is necessary to ensure any leakages which cause the  read sensing failure and degrade..

4,500.00INR
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RoBA Multiplier A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing

In this paper, we propose an approximate multiplier that is high speed yet energy efficient. The ap..

3,500.00INR
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Runtime Adaptive Circuit Switching and Flow Priority in NoC Based MPSoCs

Flip-flops and latches are used as data storage elements. Such data storage can be used for storage ..

3,500.00INR
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Stable Reliable and Bit-Interleaving 12T SRAM for Space Applications A Device Circuit Co-design

Space applications demand highly stable and reliable SRAM circuits for secure and the uninterrupted ..

3,500.00INR
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Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories

MRAM is basically used as data storage elements. Such data storage can be used for storage of state...

3,000.00INR
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Unified-VLSI-architecture-for-photo-core-transform-used-in-JPEG-XR

 Unified VLSI architecture for photo core transform used in JPEG XR’, the authors proposed a ..

4,500.00INR
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VLSI Architecture for delay efficient 8 bit Multiplier

The structure of modified tree multipliers with different adders is presented. Multiplication is an..

6,000.00INR
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VLSI Implementation of LDPC Codes

The LDPC codes are Shannon Limit codes that can achieve low bit error rates for SNR applications. Th..

6,000.00INR
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WIFI NEIGHBOR AWARENESS NETWORKING

Now days the usage of continuous-time incremental sigma-delta ADC in neural recording system is incr..

3,500.00INR
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