VLSI-CMOS
Partially Parallel Encoder Architecture for Long Polar Codes
AbstractPOLAR code means error correcting codes. This work is to implement the partial parallel enco..
Performance Analysis and Optimization for Homogenous Multi core System based on 3D Torus Network on Chip
Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip comm..
Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
Low power dissipation, low leakage current, low cost and there is required to reduce each of these. ..
Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs
It is necessary to ensure any leakages which cause the read sensing failure and degrade..
RoBA Multiplier A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
In this paper, we propose an approximate multiplier that is high speed yet energy efficient. The ap..
Runtime Adaptive Circuit Switching and Flow Priority in NoC Based MPSoCs
Flip-flops and latches are used as data storage elements. Such data storage can be used for storage ..
Stable Reliable and Bit-Interleaving 12T SRAM for Space Applications A Device Circuit Co-design
Space applications demand highly stable and reliable SRAM circuits for secure and the uninterrupted ..
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories
MRAM is basically used as data storage elements. Such data storage can be used for storage of state...
Unified-VLSI-architecture-for-photo-core-transform-used-in-JPEG-XR
Unified VLSI architecture for photo core transform used in JPEG XR’, the authors proposed a ..
VLSI Architecture for delay efficient 8 bit Multiplier
The structure of modified tree multipliers with different adders is presented. Multiplication is an..
VLSI Implementation of LDPC Codes
The LDPC codes are Shannon Limit codes that can achieve low bit error rates for SNR applications. Th..
WIFI NEIGHBOR AWARENESS NETWORKING
Now days the usage of continuous-time incremental sigma-delta ADC in neural recording system is incr..