VLSI-CMOS
11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids
Now a days, the communication industry field is mainly focused by high data transfer and more channe..
28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression
With the development of modern semiconductor fabrication technology, the channel length of the CMOS..
A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process
A 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity,..
A 16 Kb Spin-Transfer Torque Random Access Memory With Self-Enable Switching and Precharge Sensing Schemes
MRAM is basically used as data storage elements. Such data storage can be used for storage of state...
A 32 kb 0.35 1.2 V, 50 MHz 2.5 GHz Bit-Interleaved SRAM with 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS
An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage..
A 40–170 MHz PLL-Based PWM Driver Using2-/3-/5-Level Class-D PA in 130 nm CMOS
A high-speed driver that provides a pulsewidth modulated output while using a class-D Power Amplif..
A CMOS Ultra-wideband Pulse Generator for 3–5 GHz Applications
A low-power ultrawideband (UWB) pulse generator based on pulsed oscillator architecture for 3–5 GHz..
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT
Now a days, the MIMO-OFDM communication industry field is mainly focused by high data transfer and m..
A Compact-Area Low-VDDmin 6T SRAM with Improvement in Cell Stability Read Speed and Write Margin Using a Dual-Split-Control-Assist Scheme
Previous 6T SRAMs commonly employ a wordline voltage underdrive (WLUD) scheme to suppress half-sele..
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
Integral histogram image can accelerate the computing process of feature algorithm in computer vis..
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
Transpose form finite-impulse response (FIR) filters are inherently pipelined and support mu..
A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic
A high-throughput energyefficient Successive Cancellation (SC) decoder architecture for polar code..
A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops
In this process we are applying the design in D flip-flop. Because in existing itself they applied i..
A Low Cost Low Power All Digital Spread Spectrum Clock Generator
In the recent years the problem of electromagnetic interference (EMI) is increased to overcome this ..
A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks
Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing co..