Description

Many advanced multimedia applications require image compression technology with higher compression ratio and better visual quality. High quality, high compression rates of digital image and low computational cost are important factors in many areas of consumer electronics, ranging from digital photography to the consumer display equipment applications such as digital still camera and digital frame. These requirements usually involve computationally intensive algorithms imposing trade-offs between quality, computational resources and throughput. For high quality of digital image applications, the extended range of color range has becoming more important in recent emerging need of the consumer product. JPEG XR is an emerging image coding standard, based on HD Photo developed by Microsoft technology. It supports high compression performance twice as high as the de facto image coding system, namely JPEG, and also has an advantage over JPEG 2000 in terms of computational cost. JPEG XR is expected to be widespread for many devices including embedded systems in the near future. In JPEG XR image compression technique the unified photo core transform is used. It is designed to support high dynamic range and high definition formats thus this type of JPEG XR image compression with unified photo core transform is widely used in real time embedded applications. In this the parallel multiplier based photo core transform is used to lower the circuit complexity and power. In this our work is to design a photo core transform. Thus this photo core transform is implemented with adder, shifter and parallel multiplier circuits by using this the area cost and power consumption is reduced.