Description

As the technology trends to continuously shrink from small scale integration (SSI) to very large scale integration (VLSI), design for testability is also included more seriously into the ASIC flow Power models and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is pessimistic but simple for a scheduling algorithm to handle. At-speed or even faster-than-at-speed testing of VLSI circuits aims for high-quality screening of the circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, each detecting multiple delay faults, is desirable for lower test costs. On the other hand, such patterns increase switching activity during launch and capture operations. The testing architecture mainly used in all type of real world application architectures and thus the architecture to modified based on the enhancement purpose. The VLSI technology to optimize the any type of testing architecture. So the modification process used to the VLSI technology. The T-algorithm technique to optimize the testing architecture. And the architecture used to the compare the test pattern results. In this architecture, T-algorithm used to optimize the testing architecture. This architecture compare the test pattern output for the required any type of combinational architecture. The optimization process mainly focused by gate optimization for secure architecture. This process to implement the XILINX 14.2 software using VHDL language.