Description

Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing communi­cation requirements in digital systems. Network-on-chip (NoC) has emerged as a vital factor that determines the performance and power consumption of many core systems. A novel switching mechanism, called virtual circuit switching, is implemented with circuit switching and packet switching. Our work, to modify the router architecture design using the memory based selection arrangement and to design the overall NOC architecture. The 2D mesh network on chip (NOC) is a popular NOC topology because of network scalability and the use of a simple routing algorithm. However, the long distance traffic may suffer from high transmission latency. In this paper, we propose an improved design called the star-type architecture in which the long distance traffic is allowed to traverse an additional second level mesh. Simulation results demonstrate that the proposed design can reduce the number of hops traversed for long distance traffic.