Description

Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state.. Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Here, we propose a design of low power SRAM architecture using CMOS technology. The proposed memory CMOS design is based on Swapped MOS technologyIn this architecture, our work is to design a LAYOUT structure based 9T-SRAM memory design. This design is to reduce the circuit complexity level and power consumption level. Then to optimize the data storage devise and to reduce the power consumption. The portability in the electronic circuits are achieved by the use of battery. So we have make designs for low power consumption. As the technology in electronic circuits is improving, the complexity in the circuits also increases. The complexity in the circuits leads to the need of that type of circuits which are portable and fast circuits. Our proposed work is to design the 9T based SRAM layout design technique and we design a SRAM memory cell design. The read buffer of the proposed cell ensures read stability by decoupling the stored node from the read bit-line and improves read performance using a one-transistor read path. Energy and standby power are reduced by eliminating the sub-Vth leakage current in the read buffer.The proposed 9T SRAM cell has the same write operation as the conventional 6T SRAM cell. To improve the write ability ,a write-assist circuit is used. Our proposed work is to reduce the power and circuit complexity level. This work is to reduce the overall transistor count for memory cell storage operation.