Description

Low power dissipation, low leakage current, low cost and there is required to reduce each of these. To reduce device size and increasing chip density have increase the design complexity. The memories have provided the system designer with components of considerable capability and extensive application. Dynamic random access memory (DRAM) gives the advantage for high density data storage. DRAM basically a memory array with individual bit access refers to memory with both Read and Write capabilities. Here 3T DRAM is implementing with self controllable voltage level (svl) technique is for reducing leakage power. Dynamic random access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called „0‟ and „1‟. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. The main memory (the “RAM”) in personal computers is dynamic RAM (DRAM).