Description

Abstract

Dynamic random-access memory (DRAM) is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh operations waste energy and degrade system performance by interfering with memory accesses. The negative effects of DRAM refresh increase as DRAM device capacity increases. Existing DRAM devices refresh all cells at a rate determined by the leakiest cell in the device. However, most DRAM cells can retain data for significantly longer.

DRAM is one of the key products used for high-density data storage. Data retention performance is key item of DRAM product yield.

Demands have been placed on a dynamic random access memory (DRAM) to not only have increased memory capacity and data transfer speed, but also have reduced operating and standby currents. When a system uses a DRAM, a refresh

operation is necessary because of its data retention time restriction: each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor that is discharged by the leakage current. Power consumption for the refresh operation increases in proportion to the memory capacity.