Description

Embedded cores are now commonplace in large system-on-a-chip (SOC) designs. However, since embedded cores are not directly accessible via chip inputs and outputs, special access mechanisms are required to test them at the system level. A test-access architecture, also referred to as a test-access mechanism (TAM), provides the means for on-chip test data transport. Now a days, multi core processor consists of more no of complex digital architecture. This architecture is consume more circuit area and power. This type of core processor is used to many applications and to improve the application performance level. but it have some problem due to circuit complexity level. Real time application internal core processors are need more time.. So it accurs more error for internal core architecture output results. Our work is to design the low-power scan chain based parallel multi core testing architecture. This architecture is consists of different core architecture and to identify the faulty circuit using majority logic technique. Existing work is used to pipelined based TAM function for vlsi testing process. This work is to modify the test pattern generation logic using preselect logic function. The existing work is pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the design for testability based circuit test pattern generators. Proposed system is to design a multi core parallel testing architecture using majority logic technique. This technique is used to test the all internal core architecture for parallel form. This work is to implement the test pattern creation and to apply the scan chain process. This process is to analysis the separate core internal architecture output result values. The proposed system is to improve the TAM system performance level and to reduce the power consumption level also. The proposed system is used to increase the test pattern generation process.