In this proposed system is based on communication process. This design mainly consists three units. Such as transmitter unit, interconnect network and receiver unit. Those three units having clock gating, Flip flop and passive elements. Here using mux based clock gating due to that processing time will be reduced. The proposed of low power ep-DCO (Explicit Pulse –Data close to Output) flip flop solves the long discharging path problem, thus achieves better speed and power performance. The synchronous design operates at highest frequency that drives a large load because it has reach many sequential elements throughout the chip. The synchronous design operates at highest frequency that drives a large load because it has reach many sequential elements throughout the chip. Thus, clock signal have been a great source of power dissipation because of high frequency and load. Clock signals do not perform any computation and mainly used for synchronization. Hence these signals are not carrying any information. So by using clock gating one can save power by reducing unnecessary clock activities inside the gated module. The amount of power dissipation by any clock distribution system and sequential circuit in any chip is about of 30% to 60% of the total chip power dissipation by the circuit. Clock is the most important signal present in the chip. In this proposed implementation design is focused on above mentioned drawbacks. So overcome that in this design and this is done in tanner EDA tool cmos technology.