In this proposed implementation design is based on 11T and 12T SRAM cell for automotive electronics applications. In modern high performance integrated circuits, maximum of the total active mode energy is consumed due to leakage current. SRAM array is main source of leakage current since majority of transistor are utilized for on-chip memory in today high performance microprocessor and system on chip. Therefore the design of low leakage SRAM is required. In this proposed implementation is comparison of 11T and 12T SRAM cell. In the proposed 12T structure virtual vdd concept is employed because of this leakage current will reduce. Hence reduction in leakage current causes reduction in dynamic power. Power dissipation of the proposed SRAM cell have been determined and compared to those of 11T SRAM cell. The proposed design removes the half-select issue, which is a problem in SRAM array as observed in the case of conventional 10T cells. Since the proposed cell is free from half-select disturb, virtual vdd scheme can be implemented. Virtual VDD architecture helps to reduce the leakage current. And increasing the transistor count the read and write logic is improved. The design and implementation of 11-TSRAM cell to improve the read stability and read power reduction. During read operation storage nodes are completely isolated from the bit lines. The average read power consumption reduces approximately 12% compared to the 6T cell due to lower discharging activity at read bit line and low leakage current. But thus 11T structure is less performance compare with 12T SRAM cell.