ABSTRACT The Dual Mode Logic (DML) allows operation in two modes such as static and dynamic modes. DML gates, which can be switched between these modes on-the-fly, feature very low power dissipation in the static mode and high performance in the dynamic mode. A basic DML gate is very simple and is composed of any static logic family gate and an additional clocked transistor. In Proposed system we are going to develop the Logical Effort Method and will be applied in Dual mode Logic Circuit in Comparator. And in this work we are combining Pass transistor logical methodology with this DML design. Pass transistor logic (PTL) describes several logic families used in the design of integrated circuits. It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Transistors are used as switches to pass logic levels between nodes of a circuit. A comparator is a device that compares two voltages or currents and provides the outputs which is larger. A comparator used to maximize the speed and power efficiency of ADC’s (Analog to Digital converters). Comparator has two input terminals and one output terminal. The DML modification on comparator provides the low power consumption and fast operation even in small supply voltage. By adding few transistors the DML performed and the delay reduced. The reduction of delay time will provide power consumption. By this design they achieved some power consumption. Hence we are going to propose a design of CMOS PTL with DML gate based on Comparator. PTL performs a switching circuit and reduces the leakage and transistor counts. By the design they have achieved small amount of power consumption than conventional comparator. The Analysis on Comparator results are performed and Results compared between our DML with PTL comparator and Conventional comparator. The proposed methodology allows path length minimization, delay optimization, and delay estimation of DML and PTL logic. Analysis based on Approximation methods allows determining the parameter based on sizing factor and delaying optimization.