Low power issues have become an important factor in modern VLSI design. The limited power capacity systems had given rise to more power aware designs by designers. Now-a-days, power has become a crucial factor than area or speed. However, different implementation technologies present different power optimization opportunities.Low power digital Multiplier Design based on bypassing technique mainly used to reduce the switching power dissipation. While this technique offers great dynamic power savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced area and high speed advantages of tree multipliers. Therefore, mixed style architecture, using a traditional tree based part, combined with a bypass, array based part, is proposed. Prototyping of all these multiplier Architectures. A digital ADDER is a hardware electronic device that takes two numbers. Adder is used in central processing unit s and microcontrollers. The binary adder is to optimize the pattern gate count in the regular multiplier architecture based on the majority gate process. In this proposed architecture, the 8-bit multiplier pattern count is to optimize based on the majority gate architecture and to improve the 8-bit multiplier architecture performance. Multipliers play an important role in today’s digital signal processing and various other applications. In this architecture, the gate diffusion logic is used to modify the carry lookahead adder architecture based on carry delay propagation. The modified multiplier architecture to reduce the delay and area and power compare to the conventional multiplier architecture.