Description

In 3D many-core NoCs, as the network size is scaled up and the number of memory accesses increases largely, the performance (latency) gap of different memory accesses becomes bigger. Some memory accesses with very high latencies exist, thus negatively affecting the system performance. The 3D based Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing communi¬cation requirements in digital systems. 3D-Network-on-chip (NoC) has emerged as a vital factor that determines the performance and power consumption of many core systems. A novel switching mechanism, called virtual circuit switching, is implemented with circuit switching and packet switching. A path allocation algorithm is used to determine high priority based adaptive circuit switching connections and circuit-switched connections on a Fat-Tree-connected 3D-NoC, such that both communication latency and power are optimized. The system user must statically define, for example, the scheduling policy, communication priorities, and the communication switching mode of applications. The goal of this paper is to investigate the runtime adaptation of the 3D-NoC resources, according to the QoS requirements of each application running in the MPSoC. This paper adopts an NoC architecture with duplicated physical channels, adaptive routing, support to flow priorities and simultaneous packet and circuit switching. This work is to analysis the destination position level for 3D-layer based hierarchal NOC structure and to select the path using circuit switching technique. This process is to optimize the overall 3D-NOC architecture complexity level and to reduce the path delay time and clock latency time compare to existing methodology.