ENERGY EFFICIENT PROGRAMMABLE MIMO DECODER ACCELERATOR CHIP IN 65-NM CMOS
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Description
The mobile multimedia communication systems is rapid development the recent years. The main parameter is energy efficiency optimization and quality of service constraint for MIMO communication. Furthermore, the multichannel joint optimization problem in conventional MIMO-OFDM communication systems is transformed into a multi target single-channel optimization problem by grouping all sub channels. Therefore, a closed-form solution of the energy-optimization is derived for MIMO-OFDM communication systems. The various algorithm to be minimize the energy level for the Communication signal. But it have some limitation. So we used proposed energy efficiency optimized MIMO decoder accelerator to improve the energy efficiency for MIMO communication system. It targets multiple-input-multiple-output (MIMO) decoding tasks of orthogonal frequency-division multiplexing (OFDM) systems. This is implemented in most of wireless data communication systems. It delivers full compatibility across different wireless standards such as WiFi, 3G-long term evolution, WiMax and also in different MIMO decoding algorithms. The Proposed design used to solve the problem of multi-channel optimize to multi target in single channel optimization. Our proposed design consist of Basic blocks of Decoder accelerator such as memory Unit, Multiplier Unit, Adder/Subtractor unit, Rotation unit and controller parts. We optimized algorithm in Rotation unit. By using some functional conditions we implemented scheduled Rotation process. The rotation process happens randomly during the process. It describes the implementation used to ensure overall energy consumption of the designed accelerator chip without affecting programmability criteria.
Tags: 2014, Network Projects, VHDL



