An efficient hardware solution to perform table lookup is the content addressable memory (CAM). A CAM can be used as a co-processor for the network processing unit (NPU) to offload the table lookup tasks. Besides the networking equipment, CAMs are also attractive for other key applications such as translation look-aside buffers (TLBs) in virtual memory systems. Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. A special logic unit, named Multiple Match Resolver (MMR), is required to resolve the best candidate if more than one words indicate a “match”. In the early development of CAM, the capacity was small, with only a few hundred to several thousand words. The design of MMR was relatively easy, and could be realized using static digital logics. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of CAMs, high power consumption is one of the most critical challenges faced by CAM designers. This work proposes circuit techniques for reducing CAM power consumption. The main contribution of this work is divided in two parts: (i) reduction in match line (ML) sensing energy, and (ii) static-power reduction techniques. The ML sensing energy is reduced by employing (i) positive-feedback ML sense amplifiers (MLSAs), (ii) low-capacitance comparison logic, and (iii) low-power ML-segmentation techniques. Here this technique was used in CAM memory which is combined with RAM memory to enhance the performance level while searching data from memory. The focus of this work is not on the CAM memory cell design, but rather, it is on the low-power circuit techniques for multiple match resolution and detection in CAM. Both digital techniques and mixed-signal techniques are presented and analyzed in details. In RAM memory, while command was passed from CPU to RAM memory there will be address mapping was made during recovery of data. This may take much time compare to CAM memory based address fetching. In this paper, we implement the new form of hybrid RAM with CAM memory in renaming and recovering the data. Here we also implement new form of CAM architecture to improve the speed of processing. Content-addressable memories (CAMs) are hardware search engines that are much faster than modified algorithmic approaches for search-intensive applications. By this, we can search required address for single clock period. With the help of CAM architecture, we can optimize the page allocation in RAM.