The system use a coplanar QCA crossover architecture in the design of QCA full adders that leads to reduction of QCA cell count and area consumption without any latency penalty. This crossover uses non-adjacent clock zones for the two crossing wires. We further investigate the impact of these gains on carry flow QCA adders. These designs have been realized with QCA Designer, evaluated, and tested for correctness. For better performance comparison with previous relevant works, we use a QCA-specific cost function, as well as the conventional evaluation method. We show23% cell count and 48% area improvements over the best previous QCA full adder design. AS the nanometer scale CMOS devices are facing new realization challenges (e.g., increased leakage current leading to considerable static power dissipation) new technologies are emerging as possible replacements for CMOS. Quantum-dot cellular automata (QCA) represent one of such innovative platforms. The basic QCA cell, that is capable of representing a logical bit, occupies nano-scale area. QCA realization of the full adder (FA), as the most commonly used digital arithmetic cell, has been the subject of considerably many research papers . To show the impact of such very fast and low power arithmetic cell, word wide QCA adders and multipliers have been designed. One problem with designing QCA composite cells and circuits is how to efficiently design the crossover wires to reduce costs (i.e., both QCA cell count and implementation complexity). Multi-layer solution bears high cost due to, for instance, fabrication issue