Description

Tomorrow’s embedded devices need to run multimedia applications demanding high computational power with low energy consumption constraints. This system gives a efficient scheduling for reducing the leakage energy and temperature in Functional Units (FU). The energy can reduced for optimizing the instruction which will lead the temperature rising. To reduce the temperature Different algorithm was proposed in VLIW. The singular value decomposition (SVD) has recently taken on a greater significance in embedded applications but has a high computational cost. In this paper we will examine two types of high performance embedded architectures, VLIW and VIRAM, for computing the SVD. VLIW is an attractive solution due to its ability to cheaply exploit instruction level parallelism in statically schedulable algorithms. An alternative is to use a vector processor, which can exploit the high levels of vector data parallelism inherent in SVD. Vector designs can scale without increasing global interconnect or control logic. The scheduling algorithm also needs to be scalable – as the number of cores increases, the number of memory controllers shared by the cores should also increase to provide suf-ficient bandwidth to feed the cores. Unfortunately, previous memory scheduling algorithms are inefficient with respect to system through-put and/or are designed for a single memory controller and do not scale well to multiple memory controllers, requiring significant fine-grained coordination among controllers For that a novel modified Leakage-Aware Rescheduling (LARS) algorithm will be proposed. The main objective of the proposed system to propose a efficient energy consumption of the Functional Units. To optimize the power without increasing the temperatures. Shutdown the unused Functional using with priority based scheduling. A novel algorithm will be proposed with Efficient energy reduction techniques Enhance operation performed by the functional units as much as significantly.