Flip-flops are basically used as data storage elements. Such data storage can be used for storage of state. Nonvolatile memories can get back stored information even when not powered. The most widely used form of primary storage today is a volatile form of random access memory (RAM), meaning that when the computer is shut down, anything contained in RAM is lost. However, most forms of non-volatile memory have limitations that make them unsuitable for use as primary storage. Hence in Existing they were proposed the design of Magnetic flip-flop and the design is based on Check pointing/Power gating self-enable mechanism. Spin Transfer Torque MRAM (STT-MRAM) is considered as promising non-volatile memory. Which provides high speed, low power. As per existing design, during power failure or error the system recovers the data from most recent state/point. One of the disadvantages of STT-MRAM for the computing purpose is its relatively high write energy to build up Magnetic Flip-Flop (MFF). Hence in their proposed work concentrated to reduce the power consumption and write energy of MFF. Here, we propose a design of low power magnetic Flip Flop using CMOS technology. CMOS technology provide less noise ration during design. The proposed Flip flop design is based on Swapped MOS technology. Recent multi core processors require an efficient memory system to leverage the available computing power. Much of the power consumption comes from the large, multi-level, on-die cache hierarchy that most designs utilize. Spin-Torque Transfer RAM (STT-RAM) combines the speed of SRAM, density of DRAM, and non-volatility of Flash memory, making it attractive for on chip cache hierarchies. In this proposed system, we use way tag pointer for improving the enable timing in write operation in STT-MRAM Cache Architecture. STT-RAM uses magneto-resistance to encode information. This leads to high write latency compare to proposed AWARE architecture method. And our proposed design performs in retaining data when electrical power fails or is turned off with low power consumption.