Description

The digital architecture mainly used in all type of real world application architectures and thus the architecture to modified based on the enhancement purpose. The VLSI technology to optimize the any type of digital architecture So the modification process used to the VLSI technology The adder architecture used to the all type of digital architecture So modify the carry select adder architecture based on FRANKLIN Boolean logic. Carry Select Adder (CSLA) is one of the high speed adders used in many computational systems to perform fast arithmetic operations .Due to the rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified CSLA architecture has developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which replaces the BEC using D latch. Experimental analysis shows that the proposed architecture achieves the three folded advantages in terms of area, delay and power. The modified CSLA using BEC has reduced area and power consumption with slight increase in delay. The basic idea of the proposed architecture is that which replaces the BEC by D latch with enable signal. The proposed architecture reduces the area, delay and power. Based on this modification Square root CSLA (SQRT CSLA) architecture have been developed and compared with the regular and Modified SQRT CSLA architecture. The Modified CSLA architecture has been developed using Binary to Excess -I converter (BEC). This paper proposes an efficient method which replaces a BEC using common Boolean logic.