ABSTRACT Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state.. Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Here, we propose a design of low power SRAM architecture using CMOS technology. The proposed memory CMOS design is based on Swapped MOS technology. Our work, the proposed system is to design of 6T, 8T, 10T with sleep transistor based data storage architecture. Then to optimize the data storage devise and to reduce the power consumption. The continued evolution of CMOS technology beyond the 90 nm technology node will most likely be driven by advances in materials engineering and process integration. Fundamental changes in the materials used in the MOSFET gate stack will become necessary as will novel processing techniques and device structures. The performance of deep-sub-micron CMOS transistors can be improved through the use of metal gate electrodes instead of the conventional polycrystalline silicon electrodes. A major challenge in the introduction of metal gate electrodes isthe need to obtain distinct gate work functions for NMOS and PMOS devices. While two metals would ordinarily need to be used on a single silicon substrate, a method that allows the metal gate work function to be tuned over the required range is highly desirable