Product | Details | Total |
---|---|---|
![]() | Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design Rs4,500.00 As the circuit complexity increases, the number of internal nodes increases proportionally, and individual… | Rs4,500.00 |
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SubtotalRs4,500.00
9% CGSTRs405.00
9% SGSTRs405.00
Total
Rs5,310.00