Products in cart

ProductDetailsTotal
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell
Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC
Rs4,500.00
Rs4,500.00

Cart totals

SubtotalRs4,500.00
9% CGSTRs405.00
9% SGSTRs405.00