Product | Details | Total |
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![]() | Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC Rs4,500.00 The typical computer architecture for SoCs consists of one or more processors with a… | Rs4,500.00 |
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9% CGSTRs405.00
9% SGSTRs405.00
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Rs5,310.00