A Low-Power Edge Detection Image Sensor Based on Parallel Digital Pulse Computation
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Description
A pothole refers to a shallow pit on a road’s surface, caused by activities like erosion, weather, traffic and some other factors. Detecting and hence avoiding potholes may reduce the fuel consumption, wear-tear and maintenance cost of a vehicle. Also, avoiding potholes increases road safety and indirectly decreases the total travel time in some cases. We propose an edge detection algorithm which computes a route with least number of potholes which is nearest to the desired destination. If the destination is unknown, then the system will check for potholes in the current road stretch and displays the level of damage. The cracks in the road can be detected with the help of the road images. A supervised model is developed for the identification of the cracks in the road images with the help of extraction of the features from the images. In this architecture, our work is to develop the pothole detection system using edge detection technique. This work is to identify the pothole in road ways effectively compare to existing methodology. Proposed system is to design a FPGA based pothole detection system using edge detection methodology. This work is to check the selected pothole road image using reference pothole and plain road image. Proposed system is to identify the pothole and plain road position effectively and to analysis the present image and reference images. Proposed system is to segment the pothole in road images using edge detection technique. Our system is to identify pixel difference effectively and set ‘1’ and ‘0’. Proposed system is to implement sorting method and to identify the minimum data value and set the threshold data, then to apply the edge detection methodology. This proposed architecture is to optimize the internal connectivity level and to reduce memory allocation process level.