A one-pin mode transition circuit that addresses the issues related to clock synchronization in switching regulators during the mode transitions between external timing resistor and external clock. The proposed circuit reduces the circuit complexity needed to achieve mode transition during synchronization by utilizing switched-capacitor and sampling design techniques. It linearly converts the input clock frequency to a current to maintain constant amount of slope compensation for current-mode switching regulators across their switching frequency range of operation. This circuit is designed to operate from 100 KHz to 2.5 MHz and fabricated in a 0.35-μm BiCMOS–DMOS process. The total solution occupies 0.082 mm2 die area. Experimental results are presented from peak-currentmode buck regulators with one-pin synchronization circuit to show the performance improvement of using the proposed design approach over a phase-locked-loop-based design.