Description

Cryptographic processors are becoming the standard way to enforce data-usage policies. The designers wanted to prevent abuse of data and key material should a device fall into the wrong hands. From these specialist beginnings, crypto processors spread into devices such as prepayment electricity meters, and the vending machines that sell credit for them. In the last five years, dedicated crypto chips have been embedded in devices from games console accessories to printer ink cartridges, to control product and accessory aftermarkets. Research of cryptographic pairings has advanced substantially both in theory and implementation. However, due to the intricate mathematical structure, pairing requires more complicated computation than the previous public key ciphers in this project, the system presents a flexible and high-performance processor for cryptographic pairings over pairing-friendly curves at high security levels. The proposed pairing processor exploits the parallelism using three-independent pipelines, which execute basic Reduced Instruction Set Computer (RISC) instruction, F p2 multiplication, and Fp2 addition/subtraction, respectively.