The current progress in VLSI domain for the development of high performance circuits evolved the issues of transistor scaling for leakage current reduction while increasing demand for low-power VLSI circuits can be addressed at different design levels, such as the architectural, schematic, layout, and the process technology level. The logic style is a main methodology to design low power circuits. In the era of VLSI domain power consumption of high performance VLSI circuits is a major issue. There are as many as low power techniques which are used in VLSI circuits to decrease the power consumption. VLSI technology is to optimize the any type of digital architecture. Because this type of optimization process is mainly used to enhance the various applications. Now a days, most digital architectures are mainly focus by low power physical design. This type of CMOS designs are to modified circuit design. Low power reference voltage CMOS designs are to reduce the chip die area and to reduce the system power consumption level. This design is used to reduce the input voltage level. Our proposed work is to develop a voltage reference circuit design. Our work is to design bulk driven and current trimming based subthreshold voltage reference circuit. This circuit is used to reduce the operation voltage level and overall power consumption level. Then our enhancement work is compensated subthreshold CMOS design based on voltage reference circuit. This design is to reduce the transistor count level. This enhancement circuit consists of active load, voltage reference and starts up circuit level. A voltage reference circuit operating with all transistors biased in weak inversion, providing a mean reference voltage of 250 mV. This enhancement design is to reduce the overall power consumption level and to maintain the threshold voltage in any input voltage level.