Product | Details | Total |
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![]() | A 32 kb 0.35 1.2 V, 50 MHz 2.5 GHz Bit-Interleaved SRAM with 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS Rs3,500.00 An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide… | Rs3,500.00 |
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SubtotalRs3,500.00
9% CGSTRs315.00
9% SGSTRs315.00
Total
Rs4,130.00