Product | Details | Total |
---|---|---|
![]() | A 32 kb 0.35 1.2 V, 50 MHz 2.5 GHz Bit-Interleaved SRAM with 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS ₹3,500.00 An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide… | ₹3,500.00 |
Cart totals
Add coupons
9% CGST₹315.00
9% SGST₹315.00
Estimated total
₹4,130.00